1. Field of the Invention
The present invention generally relates to address translation and cache maintenance operations involving the address translation caches within a central processing unit.
2. Description of the Related Art
Computing systems often include central processing units (CPUs) to perform operations relating to the processing of data. The data processed by a processor may include instructions, which are executed by the processor, as well as data which is manipulated by the processor using the instructions. Computing systems also include memory used to store data and instructions for later use.
To provide for faster access to data and instructions, as well as better utilization of the processor, the processor may have several caches. A cache is a memory which is typically smaller than the main memory of the computer system and is typically manufactured on the same die (i.e., chip) as the processor. Modern processors typically have several levels of caches. The fastest cache which is located closest to the core of the processor is referred to as the Level 1 cache (L1 cache). In addition to the L1 cache, the processor typically has a second, larger cache, referred to as the Level 2 Cache (L2 cache).
A processor may also utilize a specialized cache to store command address translation information. Such an address translation cache (commonly referred to as a translation look-aside buffer or TLB) may store information to match the virtual address of a command to the physical address of the command. The address translation cache is used to improve the speed of translation of a virtual address to a physical address.
Due to the small size of the cache in comparison to the size of main memory, caches normally have a mechanism for invalidating entries in the cache so that the storage location can be re-used by another cache entry. This invalidation operation can be performed by hardware or software. Software invalidate operations can come in the form of a processor command or a read or a write to a register.
A problem exists when two separate input/output (I/O) devices wish to use the address translation cache at the same time. One device may desire to perform some sort of cache maintenance while another device may wish to use the cache for address translation purposes. For example, one device may desire to invalidate large groups of cache entries while another device expects uninterrupted high speed address translation. To clarify, the invalidates cause cache entries used for high speed address translation to be marked for replacement. If the large group of invalidates is received first, the later received address translation request is stalled until the large group of invalidates is finished. The stalling of a later received address translation request negatively impacts the overall performance of the processor and consequently the computing system.
Therefore, there is a need for an improved method and apparatus for allowing uninterrupted address translation while performing cache maintenance operations.